 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
|
' .
) ' ' # $ / & - ' ) # . ' ) + " $ ( ) ' ) % & * ( * * ! ' ( ( " & ' & $ " & * " & " " ) , " + * - * " + rev. d m114163 dat-31r5-pn+ 071024 page 1 of 12 product features ? dual supply voltage: v dd =+3v, v ss =-3v ? immune to latch up ? excellent accuracy, 0.1 db typ ? parallel control interface ? fast switching control frequency, 1 mhz typ. ? low insertion loss ? high ip3, +52 dbm typ ? very low dc power consumption ? excellent return loss, 20 db typ ? small size 4.0 x 4.0 mm typical applications ? base station infrastructure ? portable wireless ? catv & dbs ? mmds & wireless lan ? wireless local loop ? unii & hiper lan ? power ampli?er distortion canceling loops general description the dat-31r5-pn+ is a 50 rf digital step attenuator that offers an attenuation range up to 31.5 db in 0.5 db steps. the control is a 6-bit parallel interface, operating on dual supply voltage: v dd =+3v, v ss =-3v. the dat-31r5-pn+ is produced using a unique cmos process on silicon, offering the performance of gaas, with the advantages of conventional cmos devices. digital step attenuator 31.5 db, 0.5 db step 6 bit, parallel control interface, dual supply voltage 50 dc-2400 mhz simpli?ed schematic rf input 16db 8db 4db 2db 1db parallel control internal control logic interface latch enable 0.5db rf out dat-31r5-pn+ + rohs compliant in accordance with eu directive (2002/95/ec) the +suf?x has been added in order to identify rohs compliance. see our web site for rohs compliance methodologies and quali?cations. page 2 of 12 digital step attenuator dat-31r5-pn+ ' . ) ' ' # $ / & - ' ) # . ' ) + " $ ( ) ' ) % & * ( * * ! ' ( ( " & ' & $ " & * " & " " ) , " + * - * " + rf electrical speci?cations, dc-2400 mhz, t amb =25c, v dd =+3v, v ss =-3v absolute maximum ratings parameter ratings operating temperature -40c to 85c storage temperature -55c to 100c v dd -0.3v min., 4v max. v ss -4v min., 0.3v max. voltage on any input -0.3v min., v dd +0.3v max. esd, hbm 500v esd, mm 100v input power +24dbm parameter min. typ. max. units v dd , supply voltage 2.7 3 3.3 v v ss , supply voltage -3.3 -3 -2.7 v i dd (i ss ), supply current 100 a control input low 0.3xv dd v control input high 0.7xv dd v control current 1 a dc electrical speci?cations parameter min. typ. max. units switching speed, 50% control to 0.5db of attenuation value 1.0 sec switching control frequency 1.0 mhz switching speci?cations parameter freq. range (ghz) min. typ. max. units accuracy @ 0.5 db attenuation setting dc-1 0.03 0.1 db 1-2.4 0.05 0.15 db accuracy @ 1 db attenuation setting dc-1 0.02 0.1 db 1-2.4 0.05 0.15 db accuracy @ 2 db attenuation setting dc-1 0.05 0.15 db 1-2.4 0.15 0.25 db accuracy @ 4 db attenuation setting dc-1 0.07 0.2 db 1-2.4 0.15 0.25 db accuracy @ 8 db attenuation setting dc-1 0.03 0.2 db 1-2.4 0.15 0.25 db accuracy @ 16 db attenuation setting dc-1 0.1 0.3 db 1-2.4 0.15 0.3 db insertion loss (note1) @ all attenuator set to 0db dc-1 1.3 1.9 db 1-2.4 1.6 2.4 db input ip3 (note 2) (at min. and max. attenuation) dc-2.4 +52 dbm input power @ 0.2db compression* (at min. and max. attenuation) dc-2.4 +24 dbm vswr dc-1 1.2 1.5 1-2.4 1.2 1.5 2. input ip3 and 1db compression degrades below 1 mhz notes: 1. i. loss values are de-embedded from test board loss (test boards insertion loss: 0.10db @100mhz, 0.35db @1000mhz, 0.60db @2400mhz, 0.75db @4000mhz) page 3 of 12 digital step attenuator dat-31r5-pn+ ' . ) ' ' # $ / & - ' ) # . ' ) + " $ ( ) ' ) % & * ( * * ! ' ( ( " & ' & $ " & * " & " " ) , " + * - * " + pin description pin con?guration (top view) function pin number description c16 1 control for attenuation bit, 16db (note 3) rf in 2 rf in port (note 1) n/c 3 not connected (note 4) gnd 4 ground connection le 5 latch enable input (note 2) v dd 6 positive supply voltage pup1 7 power-up selection pup2 8 power-up selection v dd 9 positive supply voltage gnd 10 ground connection gnd 11 ground connection v ss 12 negative supply voltage gnd 13 ground connection rf out 14 rf out port (note 1) c8 15 control for attenuation bit, 8 db c4 16 control for attenuation bit, 4 db c2 17 control for attenuation bit, 2 db gnd 18 ground connection c1 19 control for attenuation bit, 1 db c0.5 20 control for attenuation bit, 0.5 db gnd paddle paddle ground (note 5) notes: 1. both rf ports must be held at 0vdc or dc blocked with an external series capacitor. 2. latch enable (le) has an internal 100k resistor to v dd . 3. place a 10k resistor in series, as close to pin as possible to avoid freq. resonance. 4. place a shunt 10k resistor to gnd 5. the exposed solder pad on the bottom of the package (see pin con?guration) must be grounded for proper device operation. pup1 gnd vss gnd gnd gnd vdd vdd pup2 rfout c8 le gnd n/c rfin c16 c4 c2 c1 c0.5 2x2mm paddle ground 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 page 4 of 12 digital step attenuator dat-31r5-pn+ ' . ) ' ' # $ / & - ' ) # . ' ) + " $ ( ) ' ) % & * ( * * ! ' ( ( " & ' & $ " & * " & " " ) , " + * - * " + typical performance curves attenuation (0.5db) @ +25c, +85c, -45c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 500 1000 1500 2000 2500 3000 3500 4000 frequency (mhz) (db) -45c +25c +85c attenuation (1db) @ +25c, +85c, -45c 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 0 500 1000 1500 2000 2500 3000 3500 4000 frequency (mhz) (db) -45c +25c +85c attenuation (2db) @ +25c, +85c, -45c 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 0 500 1000 1500 2000 2500 3000 3500 4000 frequency (mhz) (db) -45c +25c +85c attenuation (4db) @ +25c, +85c, -45c 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5 0 500 1000 1500 2000 2500 3000 3500 4000 frequency (mhz) (db) -45c +25c +85c attenuation (8db) @ +25c, +85c, -45c 7 7.2 7.4 7.6 7.8 8 8.2 8.4 8.6 8.8 9 0 500 1000 1500 2000 2500 3000 3500 4000 frequency (mhz) (db) -45c +25c +85c insertion loss (ref) @ +25c, +85c, -45c 0 1 2 3 4 5 6 7 8 0 500 1000 1500 2000 2500 3000 3500 4000 frequency (mhz) (db) +85c +25c -45c page 5 of 12 digital step attenuator dat-31r5-pn+ ' . ) ' ' # $ / & - ' ) # . ' ) + " $ ( ) ' ) % & * ( * * ! ' ( ( " & ' & $ " & * " & " " ) , " + * - * " + typical performance curves attenuation (16db) @ +25c, +85c, -45c 15 15.2 15.4 15.6 15.8 16 16.2 16.4 16.6 16.8 17 0 500 1000 1500 2000 2500 3000 3500 400 0 frequency (mhz) (db) -45c +25c +85c attenuation (31.5db) @ +25c, +85c, -45c 26 27 28 29 30 31 32 0 500 1000 1500 2000 2500 3000 3500 400 0 frequency (mhz) (db) -45c +25c +85c return loss in s11 (ref) @ +25c, +85c, -45c 0 10 20 30 40 50 0 500 1000 1500 2000 2500 3000 3500 400 0 fre q uenc y( mhz ) (db) -45c +25c +85c return loss out s22 (ref) @ +25c, +85c, -45c 0 10 20 30 40 50 0 500 1000 1500 2000 2500 3000 3500 400 0 fre q uenc y( mhz ) (db) -45c +25c +85c return loss in s11(major attenuation steps) @ +25c 0 10 20 30 40 50 60 0 500 1000 1500 2000 2500 3000 3500 4000 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db return loss out s22 (major attenuation steps) @+25c 0 10 20 30 40 50 60 0 500 1000 1500 2000 2500 3000 3500 4000 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db page 6 of 12 digital step attenuator dat-31r5-pn+ ' . ) ' ' # $ / & - ' ) # . ' ) + " $ ( ) ' ) % & * ( * * ! ' ( ( " & ' & $ " & * " & " " ) , " + * - * " + typical performance curves ip-3 input (major attenuation steps) @ +25c 0 10 20 30 40 50 60 70 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 frequency (mhz) (dbm) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db ip-3 input (major attenuation steps) @ +85c 0 10 20 30 40 50 60 70 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 frequency (mhz) (dbm) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db ip-3 input (major attenuation steps) @ -45c 0 10 20 30 40 50 60 70 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 frequency (mhz) (dbm) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db compression @input power=+24dbm (+25c) -0.8 -0.6 -0.4 -0.2 0 0.2 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db compression @input power=+24dbm (+85c) -0.8 -0.6 -0.4 -0.2 0 0.2 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db compression @input power=+24dbm (-45c) -0.8 -0.6 -0.4 -0.2 0 0.2 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 frequency (mhz) (db) att=0db att=0.5db att=1db att=2db att=4db att=8db att=16db att=31.5db page 7 of 12 digital step attenuator dat-31r5-pn+ ' . ) ' ' # $ / & - ' ) # . ' ) + " $ ( ) ' ) % & * ( * * ! ' ( ( " & ' & $ " & * " & " " ) , " + * - * " + outline drawing (dg983-1) device marking outline dimensions ( ) inch mm a bcdefghj k l m n p q r wt. grams .157 .157 .035 .008 .081 .081 .010 .022 .020 .166 .166 .070 .012 .026 .070 .04 4.00 4.00 0.90 0.20 2.06 2.06 0.25 0.56 0.50 4.22 4.22 1.78 0.31 0.66 1.78 31r5 mcl + pin 1 index date code suggested layout, tolerance to be within .002 pcb land pattern page 8 of 12 digital step attenuator dat-31r5-pn+ ' . ) ' ' # $ / & - ' ) # . ' ) + " $ ( ) ' ) % & * ( * * ! ' ( ( " & ' & $ " & * " & " " ) , " + * - * " + suggested layout for pcb design (pl-179) the suggested layout shows only the footprint area of the dat, and the components located near this area (i.e.: r1, r7). for the complete layout, see photo and schematic diagram on page 11 of 12. notes: 1. trace width is shown for fr4 with dielectric thickness. .025 .002. copper: 1/2 oz. each side. for other materials trace width may need to be modified. 2. 0603, 0402 size chip foot prints shown for reference, values of resistors will vary based on application. 3. bottom side of the pcb is continuous ground plane. denotes pcb copper layout with smobc (solder mask over bare copper) denotes copper land pattern free of soldermask page 9 of 12 digital step attenuator dat-31r5-pn+ ' . ) ' ' # $ / & - ' ) # . ' ) + " $ ( ) ' ) % & * ( * * ! ' ( ( " & ' & $ " & * " & " " ) , " + * - * " + the parallel interface timing requirements are de?ned by figure 1 (parallel interface timing diagram) and table 2 (parallel interface ac characteristics), and switching speed. for latched parallel programming the latch enable (le) should be held low while changing attenuation state control values, then pulse le high to low (per figure 1) to latch new attenuation state into device. for direct parallel programming, the latch enable (le) line should be pulled high. changing attenuation state control values will change device state to new attenuation. direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). simpli?ed schematic figure 1: parallel interface timing diagram the dat-31r5-pn+ parallel interface consists of 6 control bits that select the desired attenuation state, as shown in table 1: truth table table 1. truth table attenuation state c16 c8 c4 c2 c1 c0.5 reference 0 00000 0.5 (db) 0 00001 1 (db) 0 00010 2 (db) 0 00100 4 (db) 0 01000 8 (db) 0 10000 16 (db) 1 00000 31.5 (db) 1 11111 note: not all 64 possible combinations of c0.5 - c16 are shown in table table 2. parallel interface ac characteristics symbol parameter min. max. units t lepw le minimum pulse width 10 ns t pdsup data set-up time before clock rising edge of le 10 ns t pdhld data hold time after clock falling edge of le 10 ns t pdsup t pdhld parallel data c16:c0.5 le t lepw rf input 16db 8db 4db 2db 1db parallel control internal control logic interface latch enable 0.5db rf out page 10 of 12 digital step attenuator dat-31r5-pn+ ' . ) ' ' # $ / & - ' ) # . ' ) + " $ ( ) ' ) % & * ( * * ! ' ( ( " & ' & $ " & * " & " " ) , " + * - * " + the dat-31r5-pn+ always assumes a speci?able attenuation setting on power-up, allowing a known at- tenuation state to be established before an initial parallel control word is provided. when the attenuator powers up with le=0, the control bits are automatically set to one of four possible val- ues .these four values are selected by the two power-up control bits,pup1 and pup2 ,as shown in table 3: (power-up truth table, parallel mode). power-up control settings power-up with le=1 provides normal parallel operation with c0.5-c16, and pup1 and pup2 are not active. table 3. power-up truth table, parallel mode attenuation state pup1 pup2 le reference 0 0 0 8 (db) 0 1 0 16 (db) 1 0 0 31 (db) 1 1 0 de?ned by c0.5-c16 (see table 1-truth table) x (note 1) x (note 1) 1 note 1: pup1 and pup2 connection may be 0, 1, ground, or not con- nect, without effect on attenuation state. page 11 of 12 digital step attenuator dat-31r5-pn+ ' . ) ' ' # $ / & - ' ) # . ' ) + " $ ( ) ' ) % & * ( * * ! ' ( ( " & ' & $ " & * " & " " ) , " + * - * " + tb-340 evaluation board schematic diagram dat c0.5 c1 gnd c2 c4 c16 rfin n/c le v dd pup1 pup2 v dd gnd c8 rfout gnd gnd r7 rfin rfout c11 r8 c9 c10 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 7 dc supply j2.1 le control j1.2 c3 r1 c4 c5 c6 c7 c8 r2 r3 r4 r5 r6 vss ic 1 6 4 2 14 7 13 5 8 10 12 13 11 9 ic 2 6 4 2 14 7 13 5 8 10 12 13 11 9 r9 r10 c2 c4 c8 gnd gnd c16 c0.5 c1 12345678 gnd v dd 12 dc supply j2.2 c2 c1 + gnd le 12 ic3 parallel control j1.1 16 2 5 gnd vss v d d g n d 1234 + + c12 c13 gnd tb-340 bill of materials r1 - r8 resistor 0603 10 kohm +/- 1% r10, r11 resistor 0603 470 ohm +/- 1% r9 resistor 0402 10 kohm +/- 1% c2 - c10 & c13 npo capacitor 0603 100pf +/- 5% c1, c11 & c12 tantalum capacitor 100nf +/- 10% ic1, ic2 hex inverting schmitt trigger mm74hc14 ic3 dual non-inverting schmitt trigger sn74lvc2g17 page 12 of 12 digital step attenuator dat-31r5-pn+ ' . ) ' ' # $ / & - ' ) # . ' ) + " $ ( ) ' ) % & * ( * * ! ' ( ( " & ' & $ " & * " & " " ) , " + * - * " + tape and reel packaging information table t&r tr no. no. of devices designation letter reel size tape width pitch unit orientation 3000 t 13 inch t-005 multiples of 10, less than full reel of 3k pr 13 inch 12 mm 8 mm multiples of 10, on tape only e not applicable ordering information model no. description packaging designation letter (see table t&r) quantity min. no. of units price $ ea. dat-31r5-pn+ parallel interface, dual voltage (negative and positive) e 10 $3.80 tb-340 test board only not applicable 1 $79.95 how to order example: 3000 pieces of dat-31r5-pn+ 3k dat-31r5-pn+ t&r=t quantity model no. t&r designation letter (see table t&r) direction of feed tape cavity |
Price & Availability of 3KDAT-31R5-PNT
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |